A 2048-spin bulk acoustic wave Ising machine for number partitioning and Sudoku

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What this paper is about (big picture)

This paper introduces a new kind of problem‑solving machine, called an Ising machine, that uses tiny sound waves traveling through a piece of quartz to help find good answers to very hard puzzles. These include tasks like splitting numbers into two equal groups, solving Sudoku, and cutting a network into two parts (a classic problem called MAX‑CUT). The key idea is to use real physical waves to “compute,” which can be faster and more efficient than regular computers for these kinds of problems.

What questions the researchers asked

• Can we build a tabletop, low‑power, affordable Ising machine that’s stable in normal room temperatures?
• Can it handle lots of “spins” (think: many yes/no switches) at the same time and let every spin influence every other one (“all‑to‑all connectivity”)?
• How well does it solve standard hard problems compared to strong software methods?
• Can it tackle real‑world‑style puzzles, like number partitioning and Sudoku?

How the machine works (in everyday terms)

First, what’s an Ising machine?

• Imagine you have a bunch of switches that can be either +1 or −1 (think: on/off, yes/no). The goal is to set these switches so a score called “energy” is as low as possible. For many hard problems, the best solution matches the lowest energy.

How do they make spins using sound?

• The machine sends short radio‑frequency (RF) pulses into a quartz delay line—a solid piece of quartz where tiny “bulk acoustic waves” (small vibrations inside the material) move slowly.
• Each pulse is one “spin.” Its phase (like whether a jump rope is swinging forward or backward) represents +1 or −1.
• Many pulses are spaced out in time, one after another. This trick is called time‑multiplexing: one loop of hardware hosts thousands of spins by giving each spin its own time slot.

How do the spins talk to each other?

• A measurement‑and‑feedback system (run by an FPGA chip) quickly reads the phase (±1) of every pulse.
• Based on a programmed “who-influences-whom” table (the coupling matrix), it sends small helper pulses back into the loop to nudge each spin toward a better overall solution.
• Because the feedback can include every pair of spins, the machine has “all‑to‑all connectivity,” which is powerful for many problems.

How do they make spins stay at ±1?

• They use a phase‑sensitive amplifier (PSA). It pushes each pulse to be either 0° or 180° in phase—like snapping a switch to one of two stable positions—so the machine behaves like a set of binary spins.

Key parts they used:

• Two quartz delay lines in series (each about 707 microseconds long) at roughly 20.5 MHz.
• Short pulses, about 665 nanoseconds apart, giving 2,048 spins total.
• Off‑the‑shelf RF parts, an FPGA for fast feedback, and low overall power.

Analogy to picture it:

• Imagine 2,048 runners spaced around a circular track. Each runner carries a sign showing “+1” or “−1.” As they run laps, a coach watches all of them and shouts suggestions (feedback) to each runner about flipping or staying the same so the team’s overall score improves. After some laps, the group settles into a good (often near‑best) arrangement.

What they found and why it matters

Main results:

• Scale and precision: 2,048 spins with all‑to‑all connections and 15‑bit precision for how strongly pairs influence each other (that’s 32,768 levels).
• Speed: For a large MAX‑CUT test, it reached 90% of a strong software solver’s best energy in 341 milliseconds.
• Stability: It’s about 10,000–20,000 times more thermally stable than leading optical Ising machines. It ran on a table at room temperature without special temperature control.
• Power: About 9.6 W total; with low‑power amplifiers, about 5.9 W—pretty modest for this scale.
• Real problems: It solved number partitioning very well (often better than the software baseline) and solved full Sudoku puzzles exactly, showing the machine is flexible.
• Future speed: If run with higher‑frequency delay lines (still standard in industry), they estimate reaching similar targets in under 1 millisecond—hundreds of times faster.

Why these are important:

• All‑to‑all coupling and many spins help attack real optimization problems that grow very hard very fast.
• High thermal stability and low power make it practical—no bulky lasers, huge fiber loops, or precise temperature boxes.
• The machine not only performs competitively on a standard benchmark (MAX‑CUT) but also shines on more structured problems (number partitioning, Sudoku), which many solvers find tricky.

A short tour of the tests

• MAX‑CUT (cutting a graph into two parts to maximize the number/weight of cut edges):
  • Used large, standard test graphs (BiqMac library) with different densities.
  • Performed on par with a strong algorithm called heated ballistic simulated bifurcation (HbSB) for good approximate solutions; needed 341 ms to hit 90% of HbSB’s best in one benchmark.
  • Reached high success rates across different graph densities.
• Number Partitioning (split numbers into two groups with sums as equal as possible):
  • Across sizes 32 to 2048, the machine often beat HbSB, especially when allowing tiny approximation error (like within 0.1% of perfect).
  • This problem shows up in scheduling, chip design, cryptography, and more.
• Sudoku:
  • Encoded each cell with 9 spins (one‑hot encoding), for a total of 729 spins.
  • The machine solved full Sudoku puzzles exactly.
  • Interesting lesson: being “near” the lowest energy isn’t always enough—Sudoku needs exact rule satisfaction, so the machine had to reach the true ground state.

What this could mean going forward

• Practical, accessible hardware: Because it uses standard RF parts and runs on a bench at room temperature, it could move from labs into real‑world settings more easily.
• Faster versions are realistic: Using higher‑frequency delay lines (widely used in wireless tech) could cut times from hundreds of milliseconds to under a millisecond.
• Broad impact: Optimization crops up everywhere—logistics, finance, chip layout, drug discovery, scheduling, and more. A stable, low‑power, all‑to‑all Ising machine gives another tool for those jobs.
• Complements software: It can act like a fast, physical “optimizer” that pairs well with existing algorithms, possibly as a hybrid approach.

In short, the paper shows a stable, low‑power, affordable Ising machine using sound waves in quartz that can handle thousands of spins, solve tough problems well, and has a clear path to getting much faster—all while staying simple enough to operate on a tabletop.

Below is a concise, actionable list of the paper’s unresolved knowledge gaps, limitations, and open questions.

• Effective coupling precision is unclear: despite claiming 15-bit J_ij resolution in FPGA, the ADC/DAC are 8-bit (AD9280/AD9708), leaving the true end-to-end analog coupling resolution and quantization noise unquantified and potentially much lower than 15-bit.
• Calibration and linearity not characterized: no measurement of DAC/ADC nonlinearity, mixer (AD835) non-idealities, PSA gain-phase transfer, or overall gain/phase drift compensation, leaving the mapping from digital J_ij to injected analog c_i uncertain.
• Noise and error sources not quantified: no SNR, phase noise, timing jitter, ADC/DAC quantization noise, PSA-induced noise, or crosstalk measurements; no error budget linking these to solution quality.
• PSA binarization fidelity not measured: the “phase-sensitive attenuator + amplifier” realized via RF switches is non-ideal; its phase discrimination curve, threshold sharpness, dynamic range, and impact on spin-state error rates are not reported.
• Long-term stability and environmental robustness untested: while a lower thermal coefficient is claimed, there is no demonstration of multi-hour/day stability, performance across temperature excursions, mechanical vibrations, or aging effects.
• All-to-all computation bottleneck unaddressed: computing c_i = Σ_j J_ij s_j for N=2048 (≈2.1M terms) every circulation imposes substantial FPGA compute and memory bandwidth demands; throughput, latency, and scaling limits of the MFB pipeline are not detailed.
• Feedback latency effects not analyzed: the delay between phase measurement, digital computation, DAC output, and reinjection introduces non-negligible latency relative to the 1.41 ms circulation; its impact on convergence dynamics and stability is unmodeled.
• Update rate vs. pulse timing unspecified: how many compute/inject updates per circulation are performed, how the DAC waveform is sequenced for 2048 distinct pulses, and whether timing skew/quantization affect per-spin coupling fidelity are not described.
• Scaling beyond 2k spins lacks a concrete path: adding delay lines increases loss and complexity; higher-frequency delay lines introduce new RF/FPGA constraints; no roadmap quantifying how N scales with bandwidth, component limits, or digital resources.
• High-frequency projections omit hardware bottlenecks: the 16.455 GHz runtime projection does not account for ADC/DAC availability at those rates, FPGA compute throughput, analog component constraints (PSA switching at 2f0), increased BAW attenuation/dispersion, or mode crowding.
• Dispersion and modal issues not characterized: the delay line’s stated dispersion (50 ns) is small but not linked to pulse broadening, inter-symbol interference, or spin-to-spin uniformity; higher-frequency BAW devices may exhibit stronger dispersion and mode competition.
• Coupling strength scheduling unexplored: performance depends on coupling amplitude with an “optimal” value noted; no automatic schedule, annealing/heating protocol, or principled strategy is provided to select or adapt coupling for different instances.
• Local field (h_i) implementation and precision not characterized: the system’s ability to realize non-zero biases, their dynamic range/precision, and their effect on solution quality are not quantified (beyond Sudoku hints).
• Energy-to-solution not benchmarked: power is estimated, but energy-per-target or energy-to-solution is not compared against CPUs, GPUs, optical CIMs, or other analog machines, limiting efficiency claims.
• Benchmark breadth and fairness limited: comparison uses HbSB on a CPU only, with no baselines to strong classical heuristics (e.g., GW, SDP solvers, breakout local search) or other physics-based machines; runtime/success metrics may not be directly comparable.
• Lack of optimality certificates: for MAX-CUT and NPP, results are not compared to known optima (or tight bounds), making “approximate” solution quality hard to assess beyond HbSB-relative metrics.
• Sudoku generality and success rates unreported: only a few puzzles shown, with no statistics across difficulty levels, success probability, or time-to-solution distributions; HbSB failure may reflect mapping rather than algorithmic limits.
• Programmability and reconfiguration speed not detailed: time and overhead to load new J_ij, memory footprint for dense J (O(N²⁾ scaling), and how fast problem instances can be swapped are not specified.
• Connectivity scalability limits: while “all-to-all” is claimed, memory (∼N²⁾ and compute (∼N² per update) will dominate beyond a few thousand spins; no strategy for sparse problems, block-structured couplings, or low-rank approximations is presented.
• Coupling dynamic range constraints: the requirement that injected coupling be 5–30% of the circulating RF amplitude may limit usable J ranges and problem conditioning; no systematic study of dynamic range vs. performance is provided.
• Influence of initial conditions and reset quality not quantified: the method for erasing spin memory (briefly disabling gain) is described, but independence between runs, residual memory, and its effects on success rates are not characterized.
• Readout fidelity and misclassification rates not reported: phase detection (AD8302) accuracy, thresholding robustness, and per-spin readout error probabilities are not measured, leaving uncertainty in the reliability of reported spin states.
• Heterogeneity across spins unmeasured: amplitude and phase non-uniformity across 2048 pulses due to frequency-dependent loss or transducer variability may bias couplings; no per-spin calibration or equalization results are given.
• Sensitivity to graph structure unexplored: beyond edge density, the impact of weight distributions, community structure, degree distributions, or frustration on convergence and success rates is not analyzed.
• Lack of theoretical convergence model: the paper does not provide a dynamical model capturing the interplay of delayed feedback, PSA binarization, noise, and coupling strength to explain observed convergence or predict optimal parameter regimes.
• Robustness to faults not addressed: tolerance to component failures, bit flips in FPGA memory, ADC/DAC glitches, or switch timing errors and their effect on solution quality is unknown.
• Integration and miniaturization path unclear: the current setup uses discrete components and a large quartz disc; prospects for integrated or compact modules, packaging constraints, and manufacturability are not assessed.
• Multi-problem multiplexing and replicas: while small N replicas were mentioned for NPP, systematic methods to exploit replicas for sampling, parallel tempering, or boosting reliability are not explored.
• Real-time constraints and latency hiding: techniques to overlap computation with circulation, pipeline multiple problem instances, or exploit parallel FPGAs for larger N are not discussed.
• Comparative thermal stability lacks empirical validation: the 4-order-of-magnitude improvement is inferred from coefficients, but no controlled experiments show performance under temperature ramps or gradients compared to CIMs.
• Influence of PSA duty cycle and pulse shaping: the chosen 50% duty cycle and 6–7 carrier cycles per pulse are design choices; their optimality and trade-offs in binarization fidelity, bandwidth, and spin capacity per delay are not studied.
• Generalization to constrained problems: Sudoku illustrates that near-ground-state energies can still violate constraints; no strategies (e.g., penalty tuning, adaptive weights, constraint-specific couplings) are proposed to ensure validity in general CSPs.
• Hardware-in-the-loop reproducibility and variance: distributions of time-to-target and solution quality across many runs and multiple hardware resets (beyond histograms) are not rigorously quantified (e.g., confidence intervals, tail behavior).

Immediate Applications

Below are actionable use cases that can be deployed with the capabilities demonstrated in the paper (2048 spins, all-to-all connectivity, 15‑bit couplings, ~0.34–0.80 s solution times on MAX‑CUT with ~6–10 W power, benchtop stability using off‑the‑shelf RF components).

• Hybrid optimizer for operations research (OR) pipelines (warm-start or heuristic co-processor)
  • Sectors: logistics and supply chain, manufacturing, workforce/timetabling, cloud resource allocation
  • Tools/products/workflows: integrate the BAWIM as a service that generates near-optimal seeds for MILP/CP/MIP solvers; iterative “Ising warm-start → digital refinement” loops; use for MAX‑CUT and related QUBO/Ising problems
  • Dependencies/assumptions: problem fits within ~2048 binary variables; acceptable sub-second turnaround (~0.3–0.8 s) and stochastic outcomes; ability to map target problems to Ising/QUBO with 15‑bit weight quantization; simple API and driver software
• Electronic design automation (EDA) partitioning and floorplanning heuristics
  • Sectors: semiconductor/EDA
  • Tools/products/workflows: plugin to existing partitioners (e.g., min‑cut, graph partitioning); fast approximate graph cuts to guide placement/floorplanning or netlist clustering; ensemble runs to provide diversified solutions
  • Dependencies/assumptions: subproblem decomposition to ≤2048 spins; coupling quantization acceptable; software glue in EDA toolchains
• Balanced task assignment and load balancing via number partitioning
  • Sectors: IT/DevOps, cloud/HPC scheduling, batch processing
  • Tools/products/workflows: scheduler extension that uses BAWIM to quickly produce balanced partitions (NPP) for job queues or VM placement; near-zero discrepancy targets with high success rates demonstrated
  • Dependencies/assumptions: task sizes modeled as integers and rescaled within 15‑bit precision; batch windows tolerate ~0.3–2 s acceleration loops; post-checks for feasibility constraints
• Constraint satisfaction prototyping and education (e.g., Sudoku, CSP research)
  • Sectors: AI/optimization research, education
  • Tools/products/workflows: use Sudoku and similar CSPs to study penalty design, constraint encoding, and post-processing; classroom lab kits demonstrating physics‑based computing
  • Dependencies/assumptions: near-ground-state energy may be invalid for strict CSPs—requires penalty tuning and solution validation; one‑hot encodings increase variable count (e.g., 729 spins for 9×9 Sudoku)
• Low-power benchtop analog optimization platform for academic/industrial labs
  • Sectors: academia, corporate R&D
  • Tools/products/workflows: deploy as a reproducible hardware benchmark bed for comparing analog/digital heuristics (e.g., simulated bifurcation, simulated annealing); use for algorithm development and noise‑robustness studies
  • Dependencies/assumptions: availability of a programming interface for J/hi configuration and readout; lab staff training; mapping toolchain (QUBO→Ising→FPGA payload)
• Rapid exploration of dense, all-to-all coupling strategies in Ising/QUBO models
  • Sectors: optimization R&D, software
  • Tools/products/workflows: 15‑bit all‑to‑all couplings support testing of penalty schedules, coupling sparsification, and ensemble averaging; workflows that iterate “hardware run → digital repair”
  • Dependencies/assumptions: FPGA computation bandwidth for J·s updates at the required pulse rate; guardrails to avoid loop chaotization by injected couplings (5–30% amplitude guideline)
• Edge-friendly, energy-efficient optimizers for small facilities or SMEs
  • Sectors: small‑scale operations, makers/edtech
  • Tools/products/workflows: daily production/timetable tweaks, shift allocation, or small routing approximations with low power (~6–10 W) and no thermal control requirements; local appliance or appliance‑as‑a‑service
  • Dependencies/assumptions: moderate‑size problems (≤2048 spins); simple UIs; operator acceptance of probabilistic outputs and post‑verification
• Cryptography education and heuristic attack demonstrations
  • Sectors: academia (security/crypto)
  • Tools/products/workflows: demonstrate relationships between NPP/knapsack variants and crypto hardness; show analog heuristic performance/limits
  • Dependencies/assumptions: careful mapping and scaling; clarity that this is didactic, not a turnkey cryptanalytic tool

Long-Term Applications

These use cases require further engineering, scaling, or ecosystem development (e.g., GHz delay lines, higher-speed FPGAs/ADCs/DACs, larger spin counts, robust toolchains).

• High-frequency (GHz) BAWIM accelerators for sub-millisecond solutions
  • Sectors: data centers, finance, telecommunications (RAN scheduling), autonomous systems
  • Tools/products/workflows: PCIe/SoC cards offering real-time Ising/QUBO optimization (<1 ms TTT projected with 16.455 GHz delay lines); SDK for batch and streaming jobs
  • Dependencies/assumptions: availability of GHz BAW delay lines, custom RF front-ends, high-speed digitizers and FPGAs; careful signal integrity and thermal/mechanical design; software stack standardization
• Scaling beyond 10k–100k spins via hierarchical architectures and decomposition
  • Sectors: large-scale logistics, chip design, urban planning, national infrastructure
  • Tools/products/workflows: multi-delay-line tiling; hierarchical or divide-and-conquer QUBO solving; ensemble replica strategies with consensus/repair
  • Dependencies/assumptions: bandwidth to compute dense all-to-all terms at scale; memory and latency constraints on feedback FPGA; algorithmic decomposition preserving solution quality
• Real-time telecom resource allocation (5G/6G RAN)
  • Sectors: telecommunications
  • Tools/products/workflows: near-real-time PRB/user scheduling, beam/user grouping, interference-aware partitioning as Ising/QUBO; appliance coupled to O‑RAN controllers
  • Dependencies/assumptions: tight latency budgets; mapping fidelity for domain-specific constraints; problem sizes often >2k variables—needs scaling or decomposition; rigorous testing for SLA compliance
• Robotics and autonomous systems planning
  • Sectors: robotics, mobility, drones
  • Tools/products/workflows: on-board or edge accelerators for discrete planning subroutines (task assignment, route clustering, formation partitioning) with sub‑ms targets
  • Dependencies/assumptions: ruggedized, miniaturized hardware; strict power and vibration constraints; integration with existing planners and safety certs
• Financial combinatorial optimization (portfolio subset selection, index tracking)
  • Sectors: finance
  • Tools/products/workflows: rapid generation of diversified, near‑optimal subsets under cardinality/sector constraints using hybrid Ising‑digital loops; intraday rebalancing aids
  • Dependencies/assumptions: accurate constraint encoding; need for explainability/audit trails; numerical precision beyond 15‑bit may be necessary; compliance and reproducibility requirements
• Smart grid and energy systems optimization
  • Sectors: energy and utilities
  • Tools/products/workflows: microgrid balancing, unit commitment approximations, network partitioning to reduce losses; physics‑informed heuristics seeded into deterministic solvers
  • Dependencies/assumptions: robust constraint handling for safety and regulations; large problem sizes; validation and certification frameworks for critical infrastructure
• Drug discovery and materials design (discrete combinatorial subproblems)
  • Sectors: healthcare/life sciences, materials
  • Tools/products/workflows: QUBO mappings of scaffold selection, library design, or substructure placement as heuristic stages in larger pipelines; ensemble sampling for diversity
  • Dependencies/assumptions: high-fidelity constraint satisfaction and post‑processing; integration with domain scoring functions; spin count and precision limitations
• Network science: community detection and graph clustering at scale
  • Sectors: cybersecurity, social networks, IoT
  • Tools/products/workflows: MAX‑CUT‑like formulations for fast clustering, anomaly pre-screening; streaming modes for evolving graphs
  • Dependencies/assumptions: scalable streaming I/O; approximation acceptance; decomposition for very large graphs
• Embedded edge optimizers for IoT and industrial control
  • Sectors: manufacturing, building automation, IIoT
  • Tools/products/workflows: local, low-power combinatorial decisions (e.g., machine assignment, small routing) to reduce cloud latency and improve privacy
  • Dependencies/assumptions: ASIC/SoC integration; environmental robustness and maintenance; simple programming interfaces
• Standardization and policy for analog accelerators
  • Sectors: policy, standards bodies, funding agencies
  • Tools/products/workflows: benchmark suites and metrics (e.g., energy‑to‑target, success‑rate profiles), procurement guidelines emphasizing energy efficiency; funding for analog-centric optimization research and education
  • Dependencies/assumptions: community consensus on benchmarks and reporting; interoperable APIs across analog platforms (Ising machines, annealers, etc.)
• Consumer and educational products
  • Sectors: education, consumer electronics
  • Tools/products/workflows: kits for physics-of-computation courses; makerspace hardware for optimization challenges and puzzle solving; outreach tools to demystify analog computing
  • Dependencies/assumptions: cost-reduced designs, safety certifications, intuitive software GUIs, curated problem libraries

Cross-cutting assumptions/dependencies impacting feasibility

• Problem mapping: Many target problems must be expressed as Ising/QUBO with appropriate penalties; for strict CSPs (e.g., Sudoku), near-optimal energies can still be invalid without careful penalty engineering or digital repair.
• Scale and precision: Current hardware supports ~2048 spins and 15‑bit couplings; larger or high-precision problems require decomposition, scaling, or future hardware.
• Timing and bandwidth: The feedback path (FPGA ADC/DAC/mixer loop) must compute and inject couplings within the pulse schedule; GHz designs demand faster components and careful RF design.
• Stochastic outputs: Workflows should embrace ensemble runs and post‑selection/repair; integrate hardware results into deterministic solvers for guarantees when needed.
• Toolchain maturity: Practical adoption hinges on robust SDKs, QUBO compilers, monitoring/telemetry, and integration examples for industry-standard stacks.

• 3-dB bandwidth: The frequency span over which a device’s gain or response falls to half (-3 dB) of its peak value. "with a 3-dB bandwidth of 8 MHz centered around 20.5 MHz"
• all-to-all connectivity: A network property where every spin (node) can interact with every other spin. "Our design provides all-to-all connectivity with 15-bit coupling resolution"
• Barkhausen stability criteria: Conditions for sustained oscillation in a feedback loop: loop gain ≥ 1 and total phase shift a multiple of 2π. "This requires satisfying the Barkhausen stability criteria: the loop gain must be larger than one, and the total phase shift around the loop must be an integer multiple of $2\pi$."
• bias field: A local field term in the Ising Hamiltonian that biases a spin toward +1 or -1. "and $h_i$ is a local bias field."
• BiqMac library: A benchmark suite of graph instances commonly used for MAX-CUT and related optimization problems. "We evaluate our Ising machine using arbitrary graphs from the BiqMac library"
• bulk acoustic wave (BAW): Mechanical waves that propagate through the volume of a solid, used for RF filtering, sensing, and delay lines. "Bulk acoustic waves (BAWs) represent mechanical oscillations that propagate through the entirety of a material's volume"
• bulk acoustic wave delay line: A device using BAW propagation to create a precise signal delay. "At the core of the design is a quartz-based bulk acoustic wave 707 $\mu s$ delay line"
• Coherent Ising Machine (CIM): A photonic time-multiplexed platform that maps optimization problems to Ising dynamics. "Analog Ising machines using time-multiplexing have seen significant advancements, beginning with the demonstration of the optical Coherent Ising Machine (CIM)"
• constraint-satisfaction problems: Problems defined by variables and constraints where all constraints must be satisfied for a valid solution. "dense, non-native constraint-satisfaction problems."
• coupling matrix: The matrix J whose entries specify interaction strengths between spins in the Ising model. "The FPGA calculates the coupling pulses ($c_i$) based on the coupling matrix $J_{ij}$"
• dispersion delay: Delay variation with frequency caused by dispersion in a medium or device. "with a negligible dispersion delay $\tau _{p, disp}$ of 50 ns."
• edge density: The fraction of possible edges that are present in a graph. "Graph of the solved MAX-CUT instance with 10$\%$ edge density"
• Field-Programmable Gate Array (FPGA): A reconfigurable integrated circuit used for fast, parallelizable digital processing. "processed by an AMD Zynq ZCU104 FPGA."
• ground state: The minimum-energy configuration of a physical or computational system. "Combinatorial optimization problems are known to be mappable onto ground-state search problems of the Ising model"
• group delay: The derivative of phase with respect to frequency, representing signal propagation delay through a system. "Group delay is determined by taking the negative derivative of the phase shift with respect to frequency"
• Hamiltonian: An energy function whose minima correspond to optimal or stable configurations. "The Ising Hamiltonian is given by,"
• Heated Ballistic Simulated Bifurcation (HbSB): A physics-inspired algorithmic variant of simulated bifurcation that includes thermal effects. "we use the Heated Ballistic Simulated Bifurcation (HbSB) variant of SB"
• insertion losses: Signal power loss introduced by inserting a device into a transmission path. "with reduced insertion losses and elevated Q-factors"
• Ising energy: The value of the Ising Hamiltonian for a given spin configuration. "Figure \ref{fig:Dens10_all}(c) shows the temporal evolution of the Ising energy for multiple runs"
• Ising machine: A physical or algorithmic system designed to minimize the Ising Hamiltonian for optimization. "The Ising machines are engineered to find configurations minimizing this Hamiltonian."
• Ising model: A mathematical model with binary spins and pairwise couplings used to represent optimization problems. "Combinatorial optimization problems are known to be mappable onto ground-state search problems of the Ising model"
• MAX-CUT: A graph optimization problem seeking a partition of nodes that maximizes the sum of cut edge weights. "We evaluate the BAWIM performance using MAX-CUT problems"
• Mattis spin glass: A solvable spin-glass model with couplings structured as outer products of a pattern vector. "This Hamiltonian for NPP is similar to the Mattis spin glass Hamiltonian"
• measurement and feedback block (MFB): Hardware that measures spin states and injects computed feedback to realize couplings. "To realize the Ising machine, we developed a measurement and feedback block (MFB) similar to the CIMs"
• non-deterministic polynomial-time hard (NP-hard): A class of problems at least as hard as the hardest problems in NP, believed not to be solvable in polynomial time. "non-deterministic polynomial-time hard (NP-hard)"
• NP-complete: Problems that are both in NP and NP-hard, to which any NP problem can be reduced in polynomial time. "and NP-complete problems"
• number partitioning problem (NPP): Partitioning integers into two sets to minimize the difference of their sums. "In this section, we focus on the number partitioning problem (NPP)"
• one-hot encoding: A binary encoding where exactly one variable in a group is 1 to represent a single choice. "we represent the digits 1 through 9 in each cell using a one-hot encoding scheme"
• phase detector: A circuit that measures the phase difference between two signals. "an Analog Devices AD8302 as the phase detector"
• phase-sensitive amplifier (PSA): An amplifier whose gain depends on the input signal’s phase, enabling phase binarization. "with bistable phases achieved by phase-binarizing the propagating RF pulses using a phase-sensitive amplifier (PSA)."
• phase-sensitive attenuator: An attenuator whose transmission depends on the phase of the input signal. "The PSA comprises a phase-sensitive attenuator combined with a linear amplifier"
• Q-factor: A dimensionless measure of resonator selectivity or sharpness of resonance. "elevated Q-factors for superior frequency selectivity"
• ring oscillator: A closed-loop system where a signal circulates and oscillates based on loop gain and phase conditions. "forms a multi-physics ring oscillator."
• S-parameters: Scattering parameters describing how RF networks transmit and reflect signals at their ports. "derived from S-parameters measured using a vector network analyzer."
• Simulated Bifurcation (SB): A physics-inspired algorithm for combinatorial optimization based on bifurcation dynamics. "we use the Simulated Bifurcation (SB) algorithm"
• surface acoustic waves (SAWs): Elastic waves confined to the surface of a solid, used in RF devices. "In contrast to surface acoustic waves (SAWs), which are restricted to the substrate surface"
• thin-film transducer (TFT): A thin-film device converting electrical signals to acoustic waves (and vice versa). "An input and output thin-film transducer (TFT) is used to excite and receive propagating bulk acoustic waves."
• temperature coefficient of phase accumulation: The rate at which accumulated phase changes with temperature. "has a temperature coefficient of phase accumulation of $1.73 \times 10^7$ $deg/{^\circ} C$,"
• time-multiplexing: Representing many spins or signals sequentially in time within a shared physical medium. "Analog Ising machines using time-multiplexing have seen significant advancements"
• time-to-target (TTT): The time required to reach a specified target quality or energy threshold. "Success rate and time-to-target (TTT) of BAWIM relative to the best MAX-CUT score of HbSB."
• vector network analyzer: An instrument that measures network parameters (e.g., S-parameters) across frequencies. "measured using a vector network analyzer."
• Y-cut quartz: A specific crystal cut orientation of quartz used for piezoelectric transducers. "The microwave-to-acoustic wave transducers are made of Y-cut quartz crystal"

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