Simultaneous operation of an 18-qubit modular array in germanium

Simultaneous Operation of an 18-Qubit Modular Array in Germanium

Introduction

The scaling of spin qubit platforms in semiconductors is central to realizing fault-tolerant, utility-scale quantum computation. Device architectures must address substantial challenges including extensibility, integration with classical control, and preservation of high-fidelity coherent operation across many qubits. This work demonstrates an 18-qubit array in a Ge/SiGe heterostructure, structured as an extendable $2\times N$ modular architecture, with simultaneous initialization, control, and readout. The results represent the largest two-dimensional operational spin qubit system reported to date, providing an empirical foundation for scalable quantum dot qubit architectures.

Figure 1: False-colored scanning electron microscope image of the 18-qubit device and schematic of measurement protocols for tuning qubit states and couplings.

Architecture and Device Implementation

The demonstrated device is formed in an epitaxially grown Ge quantum well, with a triple-layer gate stack allowing semi-automated thermalization, shuttling, and parity readout. The qubit array is constructed from three modular unit-cells, each comprising six quantum dots and an associated RF charge sensor. This modularity supports linear extension and parallel operation, with minimal increase in wiring and measurement overhead with scaling.

A virtualized gate control approach is used to mitigate cross-capacitance, resulting in localized and orthogonalized voltage control over dot chemical potentials and exchange coupling. The layout supports both vertical and horizontal nearest-neighbor two-qubit gates, as verified with targeted exchange measurements across the $2\times 9$ dot grid.

Figure 3: Schematics and layouts for extendable $2\times N$ quantum dot arrays demonstrating device scalability.

Coherence, Control Fidelity, and Uniformity

Systematic benchmarking of individual qubit performance encompasses single-qubit oscillation calibration, decoherence measurements, and randomized benchmarking. Rabi chevron measurements and resonance mapping show uniform, high visibility coherent oscillations across all sites, with g-factor variations attributed to small inhomogeneities in strain or alloy composition.

Ramsey and CPMG sequence data yield an average $T_2^*$ of $6.2~\mu$s and a CPMG-extended $T_2^{\text{CPMG}}$ near $0.5~$ms, confirming that the dominant noise source remains low frequency drift, partially mitigatable by further isotopic purification and optimized global magnetic field alignment.

Randomized benchmarking quantifies a median single-qubit gate fidelity of $99.9\%$, with all qubits exceeding $99.4\%$, well above current error correction thresholds for surface codes and consistent with previous best-in-class devices (2604.01063).

Figure 4: Statistics of chevron patterns, Rabi and Larmor frequencies, and empirical cumulative distributions for $T_2^*$, $2\times 9$0, and gate error probabilities.

Figure 6: Visualization of Rabi and Larmor frequency distributions across the 18-qubit array.

Figure 2: Distribution of extracted Ramsey $2\times 9$1 coherence times, illustrating spatial uniformity and outlier identification.

Figure 9: Single-qubit randomized benchmarking traces and fidelities for all array elements.

Parallel Operation: Initialization, Control, and Readout

A core result is the demonstration of parallelized SPAM (state preparation and measurement) cycles. Initialization and readout are sequenced at the unit-cell level, with sequential steps only within a cell and strict parallelization between cells, achieving array-wide initialization without increased SPAM duration for larger arrays.

Simultaneous control is validated by performing concurrent Rabi oscillations on all even-numbered qubits, showing no significant reduction in visibility relative to individual operation, aside from minor charge sensor broadening effects. The protocol yields low classical crosstalk, with high-fidelity single-qubit addressing confirmed by systematic X-gate application and parity mapping.

Figure 10: Schematic of the multi-qubit parallel SPAM sequence and results from simultaneous versus individual qubit control.

Figure 5: Comparison of Rabi oscillation visibilities under individual and simultaneous operation, confirming parallelizability.

Two-Qubit Entangling Operations and Algorithmic Demonstration

Key to establishing universal quantum computation is the implementation of high-fidelity, tunable, two-qubit entangling gates throughout the array. Exchange-based gates are characterized for all nearest-neighbor vertical pairs, showing consistent, exponential tunability and $2\times 9$2~mV/dec response to barrier gate modulation.

An adiabatic, window-shaped voltage pulse implements CZ gates between adjacent qubits, with abuse of g-tensor modulation corrected by phase calibration routines. Calibration is further supported by repeated gate application experiments, confirming phase alignment and suppressing coherent leakage errors.

The entangling capabilities of the architecture enable preparation of a three-qubit GHZ state, using native Y and CZ gate composition. Multi-parity readout of selected vertical qubit pairs allows reconstruction of joint correlators and verification of multiqubit entanglement via controlled parity oscillation.

Figure 7: Spectroscopy of exchange couplings, tunability, CZ gate calibration, and GHZ-state generation with measured multi-qubit parity oscillations.

Figure 13: Exchange coupling tunability for three pairs involved in the GHZ preparation, highlighting precise barrier control.

Automated Calibration and Stability

An embedded calibration workflow allows daily operation with minimal manual tuning. The calibration flow automates a hierarchy of routines, including charge sensor re-optimization, Rabi calibration, drive frequency and amplitude updates, and readout state discrimination. This framework is critical for scaling experimental operation and supports reproducible benchmarked performance over extended timelines.

Figure 8: Calibration workflow diagram for the 18-qubit device, detailing the automated routines necessary to maintain high operating stability.

Discussion and Implications

This work empirically substantiates the viability of a modular, extendable, unit-cell architecture for semiconductor quantum processors. It demonstrates that all critical subroutines—SPAM, single- and two-qubit operations—can be parallelized and automated at the scale of 18 physical qubits, with crosstalk and error budgets compatible with contemporary surface code requirements. Importantly, the architecture is compatible with ongoing developments in cryogenic in-situ controllers and CMOS integration.

The uniformity of gate fidelities and coherence across a planar array provides a credible blueprint for further scaling. Integration of isotopically purified substrates, improved sensor geometries, and closed-loop tuning can further suppress dephasing and residual crosstalk. These results directly inform the path to architectures supporting hundreds or thousands of qubits, and, together with advances in error correction implementations and shuttling, move semiconductor platforms closer to practical, fault-tolerant algorithms.

Conclusion

The simultaneous operation of an 18-qubit Ge/SiGe quantum dot array affirms that modular, unit-cell device design, combined with advanced gate virtualization and calibration strategies, can achieve scalable, high-fidelity quantum control. Further development—incorporating larger arrays, isotopic engineering, and classical controller integration—will robustly address the requirements for large-scale, fault-tolerant quantum processors based on semiconductor spin qubits.

Reference:

"Simultaneous operation of an 18-qubit modular array in germanium" (2604.01063)