Experimentally verified, fast analytic and numerical design of superconducting resonators in flip-chip architectures

Analytic and Numerical Design of Superconducting Resonators in Flip-Chip Architectures

Introduction

The practical implementation of large-scale superconducting quantum processors necessitates precise and efficient electromagnetic design methodologies for integrated circuit components, particularly superconducting coplanar waveguide (CPW) resonators. As architectures move to 3D-integrated or flip-chip configurations to address wiring density and system scaling, the predictive accuracy and computational efficiency of traditional full-wave 3D simulation approaches become prohibitive bottlenecks, especially for multiplexed readout where many distinct resonators must fit within a narrow frequency band without collision. This work provides an experimentally validated methodology for designing resonators directly from 2D cross-sectional analysis, circumventing the need for time-consuming 3D electromagnetic simulation, and introduces design techniques to reduce sensitivity to inter-chip spacing variations.

Methodology: 2D Cross-Sectional Analysis

Analytic and Numerical Approach

The resonator parameters—resonant frequency ($f_r$) and coupling quality factor ($Q_c$)—are determined via two main methods:

• Conformal Mapping: The CPW cross-section is decomposed and analytically mapped to parallel-plate configurations, enabling closed-form expressions for geometric inductance ($L_l^g$) and capacitance ($C_l$).
• 2D Finite-Element Simulation: The CPW cross-section is numerically solved under quasi-TEM assumptions, taking into account finite metallization thickness and material properties, yielding $L_l^g$ and $C_l$ with high fidelity.

The frequency is then computed as:

$$f_r = \frac{1}{4l_{\text{tot}}\sqrt{(L_l^g + L_l^k)C_l}}$$

where $l_{\text{tot}}$ includes effective extension terms to model discontinuities at the ends, and $L_l^k$ is the kinetic inductance accounting for the superconducting carriers and penetration depth.

This approach leverages explicit geometric parameterization, including substrate thickness, air gap ($h_s$), and material permittivity. For kinetic inductance, magnetic penetration depth $\lambda_m$ is extracted from independent measurements, ensuring alignment with the actual superconductor properties.

Validation vs. 3D Simulation

Results from both conformal mapping and 2D simulation are compared across a range of inter-chip spacings with full 3D finite-element simulations as reference. The approach yields $<2\%$ discrepancy in $f_r$ for 6 GHz devices, establishing the quantitative correspondence between the simplified model and direct solution of Maxwell's equations for the full 3D structure.

Computation of Coupling Quality Factor

$Q_c$ is calculated using conformal mapping results for capacitances between resonator and feedline, validated via 2D cross-sectional and 3D volumetric simulations. Frequency shifts induced by coupling ($\delta f_r^c$) are also analytically modeled. For flip-chip devices, 2D analysis systematically overestimates or underestimates $Q_c$ relative to 3D by less than 20% in the relevant regime ($h_s \gtrsim 7\,\mu$m).

Experimental Verification

Fifteen resonators within a flip-chip integrated quantum processor were fabricated and measured at millikelvin temperatures. The inter-chip spacing at each resonator location was determined by SEM and compensated for via bilinear interpolation. The analytic and simulated predictions of $f_r$ and $Q_c$ show excellent quantitative agreement with measured values:

• Resonant frequency: Calculated $f_r$ matches measurement within 2% across the set, after kinetic inductance inclusion.
• Coupling $Q$: Calculated $Q_c$ values remain within $-20\%$ to $+10\%$ of measured values, with observed variation mainly attributed to wirebond-induced impedance mismatches rather than model inaccuracies.

This demonstrates that 2D cross-sectional analysis, when carefully parameterized and calibrated, is sufficient for practical precision in the design loop of superconducting quantum hardware.

Design Optimization: Robustness to Inter-Chip Spacing

The model is extended to interrogate the sensitivity of $f_r$ to inter-chip spacing, a significant source of systematic error in flip-chip layouts. The central insight is that $f_r$ responds in opposite directions for CPW segments facing a metal ground plane versus a dielectric; by engineering the ground plane with a partial cutout above the resonator, one can minimize the total frequency dependence on $h_s$. The optimal length fraction $\gamma$ of resonator exposed to dielectric is derived analytically by minimization of sensitivity across a typical $h_s$ range. 3D simulation of actual devices confirms that this approach yields $f_r$ variation $<0.2\%$ across $h_s=6$–$10\,\mu$m, substantially mitigating frequency drift due to process nonuniformity.

Computational Efficiency

An explicit benchmark comparing resource requirements reveals three orders of magnitude speedup (factor $\sim1000$) for 2D simulation relative to 3D, with memory requirements dropping from $\sim$ GB to MB scale. This computational efficiency enables scalable optimization sweeps and incorporation of large parameter splits in the design workflow, far beyond what is feasible with 3D-only approaches.

Implications, Limitations, and Future Perspectives

The transition from 3D volumetric to 2D cross-sectional simulation as the primary design tool, justified by experimental agreement, establishes a new paradigm for the parametric design of superconducting quantum hardware. The analytic underpinnings of the conformal mapping approach offer transparent scaling relations and integration into automated design toolkits and process design kits (PDKs). The method generalizes to other planar microwave elements, including couplers and Purcell filters. However, limitations remain at very small $h_s$ (breakdown of the quasi-TEM approximation and magnetic wall assumption), and for topologies with significant 3D fringing fields or airbridges.

Scalability of simulation and design is critical as processor sizes continue to increase, and high-throughput, model-driven layout and verification workflows will be essential for reliable operation. The flip-chip-insensitive resonator design motif is a concrete step towards process-tolerant qubit systems and may facilitate broader adoption in industrial-scale quantum processor fabrication.

Conclusion

This study establishes that fast, analytic and numerical 2D cross-section computations offer a highly accurate, computationally efficient alternative to 3D simulation in the design of superconducting resonators in flip-chip integrated quantum processors. Experiment supports the validity of the approach, and the development of frequency-insensitive design patterns further addresses fabrication tolerance issues. These advances enable scalable processor layout and will accelerate progress in superconducting quantum hardware while informing future developments in automated quantum hardware design systems.